PCB_Design_Manual ENE 311 : FUNDAMENTALS OF ELECTRONIC PRODUCT DESIGN Class Owner : DR.RAVIVUDH KHUN-IN Created  By:  Kittiphop Phanthachart Date :  20 August 2025   Main Drive :  Slide presentation file :  Simulation Tools Electromagnetic Field / Signal Propagation  ( For High-Speed or RF PC...

PCB_Design_Manual

เปิดวาป กิตติภพ - Google Drive

TA_ENE231/232 : Digital System - Google Drive

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TEXT BOOK FOR HARWARE_ENG - Google Drive

PCB Design Reference - Google Drive

ENE311_PCB_Design_Slide_Compressed.pdf

There is more to be thankful for in life than to regret. - XACKIES

XACKIES - Overview

Direct Digital Synthesis on FPGA with UART for Oscillator-control - XACKIES/DDS-with-Uart-interface-on-FPGA

GitHub - XACKIES/DDS-with-Uart-interface-on-FPGA: Direct Digital Synthesis on FPGA with UART for Oscillator-control

ASIC/IC-Design , Gate control of H Bridge Driver for  Motor-Drive , Non-Inverting-Buck-Boost Converter , Inverter - XACKIES/MAC101-Chip-H-Bridge-Gate-Controller-

GitHub - XACKIES/MAC101-Chip-H-Bridge-Gate-Controller-: ASIC/IC-Design , Gate control of H Bridge Driver for  Motor-Drive , Non-Inverting-Buck-Boost Converter , Inverter

Softcore MIPS Processor : Single-Cycle RISC Architecture in Verilog HDL - XACKIES/RISC-CPU-Design-of-a-Single-Cycle-MIPS-Softcore-Processor-in-Verilog-HDL

GitHub - XACKIES/RISC-CPU-Design-of-a-Single-Cycle-MIPS-Softcore-Processor-in-Verilog-HDL: Softcore MIPS Processor : Single-Cycle RISC Architecture in Verilog HDL

Designed a FIR Filter with coefficients calculated in Python and implemented fixed-point arithmetic for FPGA processing. - XACKIES/RTL-Design-of-FIR-Filter-on-FPGA-using-Verilog

GitHub - XACKIES/RTL-Design-of-FIR-Filter-on-FPGA-using-Verilog: Designed a FIR Filter with coefficients calculated in Python and implemented fixed-point arithmetic for FPGA processing.

This project implements a Digital Envelope Detector in Verilog using a first-order IIR Low-Pass filter. The detector tracks the envelope (magnitude variation) of an input signal, which is useful in RF/communication systems, AM demodulation, and signal detection. - XACKIES/RTL-Design-of-IIR-Filter-as-Digital-Envelope-Detector

GitHub - XACKIES/RTL-Design-of-IIR-Filter-as-Digital-Envelope-Detector: This project implements a Digital Envelope Detector in Verilog using a first-order IIR Low-Pass filter. The detector tracks the envelope (magnitude variation) of an input signal, which is useful in RF/communication systems, AM demodulation, and signal detection.

เอกสารประกอบการติว : https://drive.google.com/drive/folders/10dweOtMnQnOdQoErbhRUnsJlxUGU6eKg?usp=sharing

ติว ENE231/2568

MACKIES

Cocoa ,Matcha

Motion Picture Soundtrack

Stand Out Fit In

Square (2017)

We'll be fine - English Version

TEXT BOOK FOR HARWARE_ENG

ENE311_PCB_Design_Slide.pdf

MACKIES at ENE65 — KMUTT , Bachelor 

I have a lot of passion for Hardware Electronic Engineering such as FPGA, PCB design, IC-design, Image Processing, DSP and Control system design.

You can know me more from my lifestyle. I like Technology,Nature, Philosophy, History, and Cat. as “Human Being”